An All-Digital Delay-Locked Loop Using an In-Time Phase Maintenance Scheme for Low-Jitter Gigahertz Operations |
IEEE Transactions on Circuits and Systems I: Regular Papers |
Jinn-Shyan Wang; Chun-Yuan Cheng |
2015 |
A Calibration-Free PVTD-Variation-Tolerant Sensing Scheme for Footless-8T SRAM Designs |
IEEE Transactions on Multi-Scale Computing Systems |
Jinn-Shyan Wang; Yung-Chen Chien; Feng-Zhi Liu; Pei-Yao Chang
|
2015 |
A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture |
IEEE Journal of Solid-State Circuits |
Jinn-Shyan Wang; Chun-Yuan Cheng; Pei-Yuan Chou; Tzu-Yi Yang |
2015 |
Sub-threshold SRAM bit cell pnn for VDDmin and power reduction |
Electronics Letters |
Y. C. Chien; I. H. Chiang; J. S. Wang |
2014 |
Embedding Repeaters in Silicon IPs for Cross-IP Interconnections |
IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Jinn-Shyan Wang; Keng-Jui Chang; Chingwei Yeh; Shih-Chieh Chang |
2013 |
A 4R/2W Register File Design for UDVS Microprocessors in 65-nm CMOS |
IEEE Transactions on Circuits and Systems II: Express Briefs |
Pei-Yao Chang; Tay-Jyi Lin; Jinn-Shyan Wang; Yen-Hsiang Yu |
2012 |
AN ULTRA LOW-VOLTAGE/POWER-EFFICIENT ALL-DIGITAL DELAY LOCKED LOOP IN 55 nm CMOS TECHNOLOGY |
Journal of Circuits, Systems and Computers |
CHUN-YUAN CHENG, JINN-SHYAN WANG, and CHENG-TAI YEH |
2012 |
Design of 65 nm Sub-Threshold SRAM Using the Bitline Leakage Prediction Scheme and the Non-trimmed Sense Amplifier |
IEICE TRANSACTIONS on Electronics |
Jinn-Shyan WANG Pei-Yao CHANG Chi-Chang LIN |
2012 |
Towards Process Variation-Aware Power Gating |
IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Ching-wei Yeh, Yuan-Chang Chen, Jinn-Shyan Wang |
2012 |
Design of subthreshold SRAMs for energy-efficient quality-scalable video applications |
IEEE J. on Emerging and Selected Topics in Circuits and Systems |
Jinn-Shyan Wang, Pei-Yao Chang, Tai-Shin Tang, Jia-Wei Chen, and Jiun-In Guo |
2011 |
A scalable high-performance virus detection processor against large pattern set for embedded network security |
IEEE Trans. VLSI |
Chieh-Jen Cheng, Chao-Ching Wang, Wei-Chun Ku, Tien-Fu Chen*, and Jinn-Shyan Wang |
2011 |
Design of high-performance CMOS level converters considering PVT variations |
IEICE Trans. Electronics |
Jinn-Shyan Wang*, Yu-Juey Chang, and Chingwei Yeh |
2011 |
A dynamic quality-adjustable H.264 Intra Coder |
IEEE Trans. Consumer Electronics, |
Jia-Wei Chen, Hsiu-Cheng Chang, Jinn-Shyan Wang, and Jiun-In Guo |
2011 |
A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop |
IEEE Journal of Solid-State Circuits |
Jinn-Shyan Wang ; Chun-Yuan Cheng ; Je-Ching Liu ; Yu-Chia Liu ; Yi-Ming Wang |
2010 |
Heuristic Sizing Methodology for Designing High-Performance CMOS Level Converters with Balanced Rise and Fall Delays |
IEICE Transactions on Electronics |
Jinn-Shyan WANG, Yu-Juey CHANG, Chingwei YEH |
2010 |
A dynamic quality-adjustable H.264 intra coder |
IEEE Transactions on Circuits and Systems for Video Technology |
Hsiu-Cheng Chang ; Jia-Wei Chen ; Bing-Tsung Wu ; Ching-Lung Su ; Jinn-Shyan Wang ; Jiun-In Guo |
2009 |