| Half-clock frequency scheme for counter-based digital pulse-width modulator |
International Journal of Electronics Letters |
Yi-Ming Wang, Chao-Chun Chen, Yuan-Yu Shen & Chung-Hsun Huang |
2015 |
| Clock-tree aware multi-bit flip-flop generation during placement for power optimization |
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD) |
M. P.-H. Lin*, C.-C. Hsu, and Y.-C. Chen |
2015 |
| A novel analog physical synthesis methodology integrating existent design expertise |
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD) |
P.-H. Wu, M. P.-H. Lin*, T.-C. Chen, C.-F. Yeh, X. Li, and T.-Y. Ho |
2015 |
| Crosstalk-aware multi-bit flip-flop generation for power optimization |
Integration, the VLSI Journal |
C.-C. Hsu, M. P.-H. Lin*, and Y.-T. Chang |
2015 |
| Thermal-aware code transformation across functional units |
Concurrency and Computation: Practice and Experience |
Chia-Jung Chen, Rong-Guey Chang |
2015 |
| A Virtualization Approach to Develop Middleware for Ubiquitous High Performance Computing |
Computers and Electrical Engineering |
Jen-Chieh Chang, Chia-Jung Chen, Rong-Guey Chang |
2015 |
| A priority scheduling for TM pathologies |
The Journal of Supercomputing |
Chia-Jung Chen, Rong-Guey Chang |
2015 |
| Partial parity cache and data cache management method to improve the performance of an SSD-based RAID |
IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Ching-Che Chung* and Hao-Hsiang Hsu |
2014 |
| High-resolution all-digital duty-cycle corrector in 65-nm CMOS technology |
IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Ching-Che Chung*, Duo Sheng, and Sung-En Shen |
2014 |
| Block-Wise QR-Decomposition for the Layered and Hybrid Alamouti STBC MIMO Systems: Algorithms and Hardware Architectures |
IEEE TRANSACTIONS ON SIGNAL PROCESSING |
Tsung-Hsien Liu, Chun-Ning Chiu, Pei-Yu Liu, and Yuan-Sun Chu |
2014 |
