An All-Digital Delay-Locked Loop Using an In-Time Phase Maintenance Scheme for Low-Jitter Gigahertz Operations |
IEEE Transactions on Circuits and Systems I: Regular Papers |
Jinn-Shyan Wang; Chun-Yuan Cheng |
2015 |
A Calibration-Free PVTD-Variation-Tolerant Sensing Scheme for Footless-8T SRAM Designs |
IEEE Transactions on Multi-Scale Computing Systems |
Jinn-Shyan Wang; Yung-Chen Chien; Feng-Zhi Liu; Pei-Yao Chang
|
2015 |
A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line Architecture |
IEEE Journal of Solid-State Circuits |
Jinn-Shyan Wang; Chun-Yuan Cheng; Pei-Yuan Chou; Tzu-Yi Yang |
2015 |
A Fully-Integrated Wireless Bondwire Accelerometer With Closed-loop Readout Architecture |
IEEE Transactions on Circuits and Systems I: Regular Papers |
Yu-Te Liao; Shih-Chieh Huang; Fu-Yuan Cheng; Tsung-Heng Tsai |
2015 |
Half-clock frequency scheme for counter-based digital pulse-width modulator |
International Journal of Electronics Letters |
Yi-Ming Wang, Chao-Chun Chen, Yuan-Yu Shen & Chung-Hsun Huang |
2015 |
Clock-tree aware multi-bit flip-flop generation during placement for power optimization |
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD) |
M. P.-H. Lin*, C.-C. Hsu, and Y.-C. Chen |
2015 |
A novel analog physical synthesis methodology integrating existent design expertise |
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE TCAD) |
P.-H. Wu, M. P.-H. Lin*, T.-C. Chen, C.-F. Yeh, X. Li, and T.-Y. Ho |
2015 |
Crosstalk-aware multi-bit flip-flop generation for power optimization |
Integration, the VLSI Journal |
C.-C. Hsu, M. P.-H. Lin*, and Y.-T. Chang |
2015 |
Thermal-aware code transformation across functional units |
Concurrency and Computation: Practice and Experience |
Chia-Jung Chen, Rong-Guey Chang |
2015 |
A Virtualization Approach to Develop Middleware for Ubiquitous High Performance Computing |
Computers and Electrical Engineering |
Jen-Chieh Chang, Chia-Jung Chen, Rong-Guey Chang |
2015 |